Silicon carbide (SiC) is a semiconductor material the application of which to a next-generation low-loss power device or the like is expected because it features a larger band gap than silicon (Si) and a higher field intensity at which a dielectric breakdown occurs. Silicon carbide has numerous polytypes including cubic-type 3C—SiC and hexagonal-type 6H—SiC and 4H—SiC. Of these polytypes, 6H—SiC and 4H—SiC are used commonly to produce practically usable silicon carbide semiconductor devices. Among them, a silicon carbide substrate (SiC substrate) having a principal surface which is substantially coincident with the (0001) plane perpendicular to the crystal axis of the c-axis is used mostly for a silicon carbide semiconductor device (SiC semiconductor device).
To form a silicon carbide semiconductor device, it is necessary to form an epitaxially grown layer serving as the active region of the semiconductor device on a silicon carbide substrate and control the conductivity type and carrier concentration of a selected region in the epitaxially grown layer. To form an impurity doped layer in the selected local region, a technology which ion-implants an impurity dopant into the epitaxially grown layer is used.
A description will be given herein below to a typical method for forming a MOSFET made of silicon carbide by using the ion implantation technology.
FIGS. 9(a) to 9(d) are cross-sectional views illustrating the typical method for forming the MOSFET made of silicon carbide.
First, in the step shown in FIG. 9(a), a silicon carbide thin film is epitaxially grown on a silicon carbide substrate 140 to form an n-type drift layer 141. In this step, the density of steps in the surface of the substrate is increased by intentionally imparting a slight angle (at several degrees) to the (0001) plane of the silicon carbide substrate 140 so that the silicon carbide thin film is grown by a step flow process which involves the lateral growth of the steps. At present, it is common practice to impart an off-angle of 8° to 4H—SiC and an off-angle of 3.5° to 6H—SiC, each in the [11-20] direction by using the (0001) plane as a reference plane.
Subsequently, in the step shown in FIG. 9(b), an implant mask 142 for ion implantation is formed on the upper surface of the n-type drift layer 141. The implant mask 142 covers a portion of the n-type drift layer 141 such that a region, which will serve as a p-type well region 143 in the subsequent step, is opened.
Next, in the step shown in FIG. 9(c), Al ions 144 are implanted into the n-type drift layer 141 from above the implant mask 142.
Then, in the step shown in FIG. 9(d), the implant mask 142 is removed. Thereafter, an activation annealing process is performed by heating the silicon carbide substrate 140 in an inert gas (e.g., argon gas) atmosphere to a temperature not lower than 1700° C. to recover the damage caused by the ion implantation and activate the implanted impurity ions. By the activation annealing process, a p-type well region 143 is formed in a part of the n-type drift layer 141.
By subsequently performing additional ion implantation and the formation of electrodes, a vertical MOSFET can be fabricated.
However, since the silicon carbide substrate is processed at a high temperature in the step shown in FIG. 9(d), macro-steps 145 are formed disadvantageously in the upper surface of the region into which the ions have been implanted. In addition, macro-steps 146 are also formed in the upper surface of the region into which ions have not been implanted, though the macro-steps 146 are smaller in size than the macro-steps 145 in the ion implanted region. A macro-step is a bunch of combined steps each formed at a depth corresponding to several atomic layers in the surface of a silicon carbide thin film. In a prior art technology as shown in FIGS. 9, projections and depressions formed due to the macro-steps in the upper surface of the silicon carbide thin film after the activation annealing have presented a great obstacle to an improvement in the performance of the semiconductor device. A conceivable reason for the macro-steps 145 formed in the ion implanted region which are larger in size than the macro-steps 146 formed in the region without ion implantation is that the damage caused by the ion implantation has rendered silicon atoms and carbon atoms more likely to be desorbed from the surface of the silicon carbide thin film. The size of each of the macro-steps 145 is larger as the temperature for the activation annealing is higher. There are cases where a step height (see FIG. 9(d)) reaches several tens of nanometers and the width of a terrace reaches several hundreds of nanometers.
The formation of the macro-steps has caused performance degradation in numerous semiconductor devices including a MOSFET. In the case with, e.g., a Schottky diode, the problem is encountered that the localization of an electric field to the tip portions of macro-steps occurs in a Schottky electrode formed on the upper surface of a silicon carbide thin film and the breakdown voltage thereof is thereby lowered. In the case with a MESFET in which a current flows in the surface layer of a silicon carbide thin film, the problem is encountered that the disturbance of carriers occurs in macro-steps to lower mobility and reduce transconductance. A MOSFET in which a gate oxide film is formed by thermal oxidation on the upper surface of a silicon carbide thin film encounters the problem that the formation of an oxide film having different thicknesses at the sidewall and terrace portions of macro-steps causes the non-uniform thickness of an inversion layer formed by applying a gate voltage and the lowering of channel mobility. Thus, in accordance with the conventional method, even when a semiconductor device is produced by using silicon carbide, it has been difficult to obtain electric characteristics expected from the inherently excellent physical property values of silicon carbide.
To prevent the steps from being formed in the upper surface of a silicon carbide thin film by activation annealing, it has been proposed to form a diamond-like carbon (DLC) film or a photoresist as a protective film on the upper surface of the silicon carbide thin film prior to the activation annealing (see, e.g., Patent Document 1).
Patent Document 1: Japanese Laid-Open Patent Publication No. 2001-68428